Yogesh Singh Chauhan
(MT/EE/2003)
Prof. Yogesh Singh Chauhan is a Professor in the Department of Electrical Engineering at IIT Kanpur and an IEEE Fellow. He is also the Chair Professor of the Shri Jagdeo Narain Gupta & Smt. Murti Devi Gupta Chair at IIT Kanpur.
Profile
His research focuses on nanoelectronics, particularly the compact modeling of advanced semiconductor devices, including Bulk and SOI MOSFETs, multigate FETs, nanowire devices, UTBSOI, and emerging device architectures. He is actively engaged in the development and support of the industry-standard ASM-HEMT model and has contributed to BSIM model development in collaboration with the BSIM Group at the University of California, Berkeley. His expertise further includes atomistic simulation of nanoscale devices, DC, CV, and RF characterization of MOSFETs, and the application of machine learning methodologies to semiconductor device research and modeling.
He has held several key academic and professional leadership positions, including Head of the Department of Electrical Engineering at IIT Kanpur (2024-2027) and Associate Dean, Physical Infrastructure-II (2022-2024). Within IEEE, he has served as Chairperson of the IEEE U.P. Section (2024-2025), Vice-Chairman (2018-2019), Chairperson of the IEEE-EDS Conference Engagement Working Group (2024), and Chairperson of the IEEE EDS Compact Modeling Committee (2021-2024). He is also the Founding Chairperson of the IEEE Electron Devices Society, U.P. Chapter, Kanpur, and has contributed as Executive Committee Member and Convener of multiple committees. At IIT Kanpur, he has additionally served as Convener of the Department Postgraduate Committee, Member of DPGC, and Warden of Hall 10.
Prof. Chauhan received his B.E. from Shri Govindram Seksaria Institute of Technology and Science, Indore, in 2001, followed by an M.Tech. in Microelectronics and VLSI from IIT Kanpur in 2003. He earned his doctorate from Switzerland in 2007. He began his professional career as an Associate Design Engineer at ST Microelectronics, Noida (2003-2004), and subsequently served as Manager of Modeling, Physical Design, and Design Automation at IBM's Semiconductor Research and Development Center, Bangalore (2007-2010). In 2010, he was associated with Tokyo Institute of Technology, where he worked on modeling and simulation of nanoelectromechanical FETs. He later carried out his postdoctoral research at the University of California, Berkeley, where he also served as BSIM Program Manager, before joining IIT Kanpur as an Assistant Professor in 2012.
Achievements and Honors
- Fellow, Indian Academy of Sciences, 2026
- Chair Professor, Shri Jagdeo Narain Gupta & Smt. Murti Devi Gupta Chair, 2024
- Visiting Professor, Technical University of Munich, Germany, 2024
- Class of 1984 Chair Professorship, IIT Kanpur, 2021-2024
- Fellow, Institute of Electrical and Electronics Engineers (IEEE), USA, 2021
- Fellow, Indian National Academy of Engineering (INAE), 2021
- VASVIK Industrial Research Award 2020 in Electrical & Electronic Sciences & Technology, 2021
- Member, Indian National Young Academy of Science (INYAS), 2018-2022
- Swarna Jayanti Fellowship, 2018
- Humboldt Fellowship, 2018
- IETE S. K. Mitra Memorial Award, 2018
- C. N. R. Rao Faculty Award, 2018
- ASM-HEMT compact model for GaN HEMTs selected as the first industry standard model by the Si2 Compact Model Coalition, 2018
- P. K. Kelkar Research Fellowship, 2015
- IBM Faculty Award, 2013
- Ramanujan Fellowship, Department of Science and Technology, 2012
- Honorable Mention Award, IEEE VLSI Conference, January 2008