Special Manpower Development Programme in VLSI
    Phase - 2

IEP3 Course on Low Power Digital Design. September 24-28, 2012

  1. Schedule iep3
  2. Low Power Digital Design Lecture Day 2
  3. L5-L6-SiliconProcessing
  4. MOSFET_Models_1_MOS_Cap
  5. MOSFET_Models_2_MOS_Modeling
  6. MOSFET_Models_3_Advanced_Modeling
  7. MOSFET_Models_4_SPICE
  8. MOSFET_Models_5_Scaling
  9. MOSFET_Models_6_MultiGate
  10. MOSFET_Models_7_NewModels

 
 

Topics & Links

India Chip Digital ASIC

The India Chip is to promote ASIC design activity at other engineering colleges in the country. The digital designs from five different institutions have been integrated together at IIT Kanpur on a single chip.   Read more ..