 | IIT Kanpur |
The SMDP Program in VLSI was initiated and funded by the Ministry of Communications and Information Technology, Government of India in year 1999. The first phase of this program was successfully completed in March 2005. The second phase of this program was started in April 2006 with IIT Kanpur as one of the Resource Centre.
You can find more from MCIT SMDP2 Site.
The objective of this program is to strengthen the VLSI activities across the country with the establishment of VLSI Design Labs at Resource Centres and Participating Institutions by giving training to graduate, post graduate and doctoral levels.
The VLSI-EDA Lab in the Department of Electrical Engineering has been funded by SMDP1, SMDP2 and the Department itself. The Lab has been provided with all necessary VLSI-EDA software and hardware tools, test and measurement instruments, computing facility and an in-house library.
The list of EDA tools include Cadence Virtuoso IC design package for Analog/ Mixed Signal/ RF designs, Synopsys RTL-GDSII system design suite with HSPICE and TCAD, Mentor Graphics IC AMS design package, Coware system architecture and signal processing package, Magma RTL-GDSII tool and Xilinx ISE Design Suite with Spartan3 and Virtex-4 Kits. All tools are equipped with process technologies from 350nm to 45nm node.
The India Chip is to promote ASIC design activity at other engineering colleges in the country. The digital designs from five different institutions have been integrated together at IIT Kanpur on a single chip. 
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