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Advertisement Number: P.Rect./R&D/2026/013
Established in 1959, IIT Kanpur is one of the most prestigious institutes in the country. With the best research infrastructure and state-of-the-art facilities, it encourages students to innovate using technology and approach education with a problem-solving attitude. It was set up with a vision to create, disseminate and translate knowledge in science, engineering, and allied disciplines that will best serve the society; and the recognition that the Institute has garnered as a major center of learning in Engineering, Science, and several Inter-disciplinary Areas is a testament to the success of this vision.
Project Overview:
Join an innovative team at IIT Kanpur to develop a high-performance production compiler targeting an advanced RISC-V DSP and AI compute architecture with a 256-bit SIMD vector engine. This effort is crucial for enabling next-generation 6G communication systems and requires designing, optimizing, and implementing cutting-edge compiler technologies.
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(a)
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Position
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Project Scientist
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(b)
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No. of positions
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02
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(c)
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Location
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IIT Kanpur
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(d)
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Eligibility
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- Strong understanding of instruction-level parallelism, code generation, and optimization techniques for SIMD/vector architectures.
- Proficient with C/C++ and systems programming languages; experience with Rust is an advantage.
- Demonstrated ability to work collaboratively in multi-disciplinary teams and deliver on project milestones.
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(e)
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Desired qualification
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- Master’s or PhD in Computer Science, Electrical Engineering, or a related technical discipline with specialization in compiler design, software optimization, or embedded systems.
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(f)
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Experience
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- 3+ years professional experience in compiler development, preferably with LLVM.
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(g)
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Desired Skills
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- Background in DSP algorithms and domain-specific optimization.
- Familiarity with multi-pipeline and multi-issue processor architectures.
- Knowledge of software development life cycle practices including version control, automated testing, and build systems.
- Excellent analytical, problem-solving, and communication skills.
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(h)
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Consolidated Salary range
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Rs. 31600 TO 78400/-
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(i)
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Working hours
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9.30 am - 6.00 pm
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(j)
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Roles and Responsibilities
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- Design and develop key components of the LLVM backend for the DSP architecture, including instruction selection, scheduling, and register allocation specialized for multi-pipeline SIMD vector processors.
- Implement advanced compiler optimization passes focusing on vectorization, instruction-level parallelism, and domain-specific transformations for DSP algorithms.
- Work with front-end teams to enable effective language support and intrinsics for C, C++, and Rust.
- Participate in the integration of debugging support, testing frameworks, and continuous integration pipelines to ensure compiler quality and stability.
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(k)
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Appointment
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Initially for a period of 01 year, extendable yearly as per the project duration
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(l)
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Application Process
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(m)
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Last date of receipt of application
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Jan 28, 2026 (Tentative)
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No hard copies of applications will be accepted.
Note: The institute reserves the right to fix suitable criteria for short listing of eligible candidates satisfying qualification and experience. Only shortlisted candidates will be called for the test/interview. No TA/DA will be paid for attending the test/interview.
Dr Amey Karkare Professor,
Dept. of CSE, IIT Kanpur
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