Special Manpower Development Programme in VLSI
    Phase - 2

Instruction Enhancement Program

  1. IEP1 Course on Digital IC Design. July 03 - 14, 2006
  2. IEP2 Course on Synthesis of Digital Systems. December 10 - 27, 2007
  3. IEP3 Course on Low Power Digital Design. September 24 - 28, 2012

Training Program

  1. Synopsys EDA Tool Training Workshop. September 20 - 24, 2008
  2. Cadence Tool Training Course for India-Chip 2010 Tapeout. June 29 - July 04, 2009

ZOPP Workshop

  1. 3rd ZOPP Workshop. February 11 - 13, 2008
  2. 7th ZOPP Workshop. February 10 - 11, 2012

 
 

Topics & Links

India Chip Digital ASIC

The India Chip is to promote ASIC design activity at other engineering colleges in the country. The digital designs from five different institutions have been integrated together at IIT Kanpur on a single chip.   Read more ..