Department of Electrical Engineering

Advertisement Number: P.Rect./R&D/2022/015

Applications are invited for two posts of Senior Project Engineers. These positions will be up to December 31, 2024, and purely temporary.

About the project: Department of Technology (DOT) has funded Maintaining the Indigenous 5G Test Bed project to enhance the 5G testbed which has been designed at IIT Kanpur. This project envisages to not only maintain the testbed but also make it ready for the future 5G+/6G standard. All activities in this project are focused towards creating IPRs which lead to designing algorithms that will make up the product design and implementation IPRs that can give a head start in developing 5G+/6G telecom products.

What is involved? Designing and analysing physical layer algorithms for 5G+/6G standard in MATLAB and C and testing these algorithms on in-house 5G test bed. Understanding the future releases of the 5G NR standard.

Job Description:

Project No. DOT /EE /2021333

Post:Senior Project Engineers

Number of Post: Two

Salary range: 32400-2700-81000

Min Qualification: B.Tech + M.Tech + PhD (Electronics/Communication Engineering) Or M. Tech (Electronics/Communication Engineering) with 3 years of experience in the relevant area. Candidates with lower qualification might also be considered if they have a highly relevant experience.

  • Excellent background in wireless communication
  • Deep understanding of communication theory, modulation schemes, receiver design, MIMO techniques
  • Extensive expertise in MATLAB and C programming in designing and simulating communication systems

Desirable Qualification for algorithm development: 

  • Knowledge of 4G/5G standards
  • Extensive experience in developing PHY layer algorithms preferably in MATLAB/C
  • Understanding of various wireless technologies such as massive MIMO, mmWave, non-orthogonal multiple access (NOMA), unmanned aerial vehicles (UAVs)
  • Desirable Qualification for embedded code development:
  • Analog and digital board testing and integration
  • Porting of 5G+/6G physical layer algorithms on FPGA
  • Real-time testing of algorithms on the 5G testbed
  • Embedded design of hardware interfaces

Responsibilities: To

  • Design physical layer algorithms for 5G PHY layer
  • Analyse system-level performance of 5G standard by executing system-level simulations
  • Use existing system level simulators and enhance them with the novel technologies.

Instructions to apply:

Please send your resume on or before Jan 28th, 2022, to the below given mail id. Please [mention the post in the subject line of the email].

No TA/DA will be paid for the interview.


Dr. Rohit Budhiraja
Project Investigator
Room no-ACES-201A
Department of Electrical Engineering
Indian Institute of Technology Kanpur