Department of Electrical Engineering

Advertisement Number: P.Rect./R&D/2019/255

Applications are invited for two post of Senior Project Associate. This position will be up to March 21, 2021 and purely temporary.

About the project: The Department of Telecommunications (DoT) has funded 5G testbed project to encourage Indian start-ups and the industry to take an early lead in 5G technology. The goal of the project is to build a testbed that closely resembles a real-world 5G deployment. The project will deliver an end-to-end 5G testbed comprising of 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC) and massive MTC including NB IoT services. This testbed could become a basis for many commercial deployments.

What is involved?

This involves designing and fabricating multiple high-end components such as baseband processing units, remote radio heads, RF modules, and baseband algorithms and software.

Who is involved?

Top Indian Institutes and start-ups such as IITK, IITD, IIT M, IISc, Sameer, and CEWiT are involved in this project. Many private companies are also a part of this effort.

Job Description:

Project no.:DOT/EE/2017508

Post: Senior Project Associate

Number of Post: Two

Salary range: 21600-1800-54000

Min. Qualification: B.Tech- Computer Science/Electronics & Communication Engg

+ 1 year of relevant experience

  • Expertise in Verilog/VHDL

Desirable Qualification:

  • Experience in working with Xilinx programmable SoC/FPGA
  • Experience in using timing constraints
  • Knowledge of AXI4
  • Working knowledge of C language
  • Background in wireless communication will be preferred
  • Excellent interpersonal, written and verbal communication skills

Job Responsibilities:

  • Design and verification of Xilinx FPGA-based intellectual property (IP) blocks
  • Integration & debugging of subsystems within Xilinx SoC environment

Instructions to apply:

Please send your resume on or before Aug 2nd, 2019 to the below given mail id. Please[mention the post in the subject line of the email].

No TA/DA will be paid for the interview.


Dr.Rohit Budhiraja
Project Investigator
Room no-ACES-201A
Department of Electrical Engineering
Indian Institute of Technology Kanpur