Faculty Profile  

Complete List of Publications

  1. S.E. Pratsinis, G. Wang, S. Panda, T.Guiton, A.W. Weimer, "Aerosol Synthesis of AlN by Nitridation of Aluminum Vapor and Clusters", J. Mat. Res., 10, 512 (1995).
  2. S. Panda, S.E. Pratsinis, "Modeling the Synthesis of Aluminum Particles by Evaporation - Condensation in an Aerosol Reactor", Nanostructured Materials, 5, 755 (1995).
  3. L. Gradon, S.E. Pratsinis, A. Podgorski, S.J. Scott, S. Panda, "Retention of Inhaled Particles in Rat Lungs Including Toxic and Overloading Effects", J. Aerosol Sci., 27, 487 (1996).
  4. S. Panda, J.S. Kim, B.H. Weiller, D.J. Economou, D.M. Hoffman, "Low Temperature Chemical Vapor Deposition of Titanium Nitride Films from Tetrakis(ethylmethylamido)titanium and Ammonia", Thin Solid Films, 357, 125 (1999).
  5. S. Panda, D.J. Economou, M. Meyyappan, "Effect of metastable oxygen molecules in high density power-modulated oxygen discharges", J. Appl. Phys., 87, 8323 (2000).
  6. S. Panda, D.J. Economou, L. Chen, "Anisotropic etching of polymer films by high Energy (~100s of eV) oxygen atom neutral beams", J. Vac. Sci. Technol. A, 19, 398 (2001).
  7. R. Wise, S. Panda, S. Mathad, R. Ranade, "Observations of Pattern-Dependent Plasma Charging and Polymer Deposition During Deep Trench Dry Etch", Future Fab International, 249, 11 (2001).
  8. S. Panda, R. Wise, "Etch Characteristics and Challenges of Silicon Deep Trench Module", Business Briefing: Global Semiconductor Manufacturing Technology, 2003, 32 (2003).
  9. S. Panda, R. Ranade, G.S. Mathad, "Etching High Aspect Ratio Silicon Trenches", J. Electrochem. Soc., 150, G612 (2003).
  10. S. Panda, R. Wise, A. Mosden, K. Sugiyama, J. Camilleri, "Effect of Rare Gas Addition on Deep Trench Silicon Etch", Microelectronic Engr., 75, 275 (2004).
  11. H.S. Yang et al. (with S. Panda), "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing", IEDM Tech. Digest, 1075 (2004).
  12. S. Panda, R. Wise, A. Mahorowala, V. Balasubramanian, K. Sugiyama, "Etching Silicon-containing Bilayer Resists in Ammonia-based Plasmas", J. Vac. Sci. Technol. B, 23, 900 (2005).
  13. Q. Ouyang, M.Ieong, M. Fischetti, S. Panda, D. Boyd, K. Rim, J.A. Ott, "Characteristics of High Performace PFETs with Embedded SiGe Source/Drain and <100> Channels on 45' Rotated Wafers", VLSI-TSA Tech. Digest, 27 (2005).
  14. C.D. Sheraw, M. Yang, D.M. Fried, G. Costrini, T. Kanarsky, W.-H. Lee, V. Chan, M.V. Fischetti, J. Holt, L. Black, M. Naeem, S. Panda, L. Economikos, J. Groschopf, A. Kapur, Y. Li, R. T. Mo, A. Bonnoit, D. Degraw, S. Luning, D. Chidambarrao, X. Wang, A. Bryant, D. Brown, C.-Y. Sung, P. Agnello, M. Ieong, S.-F. Huang, X. Chen, M. Khare, "Dual Stress Liner Enhancement in Hybrid Orientation Technology", VLSI Tech. Digest, 12 (2005).
  15. Q. Ouyang, M. Yang, J. Holt, S. Panda, H. Chen, H. Utomo, M. Fischetti, N. Rovedo, J. Li, N. Klymko, H. Wildman, T. Kanarsky, G. Costrini, D.M. Fried, A. Bryant, J.A. Ott, M. Ieong, C.-Y. Sung, "Investigation of CMOS Devices with Embedded SiGe Source/Drain on Hybrid Orientation Substrates", VLSI Tech. Digest, 28 (2005).
  16. E. Leobandung et al. (with S. Panda), "High Performance 65 nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM cell", VLSI Tech. Digest, 128 (2005).
  17. W.-H. Lee et al. (with S. Panda), "High Performance 65 nm SOI Technology with Enhanced Transistor Strain and Advanced-Low-K BEOL", IEDM Tech. Digest, 61 (2005).
  18. Z. Luo, Y. Chong, J. Kim, B. Greene, S. Panda, T. Sato, J. Holt, D. Chidambarrao, J. Li, R. Davis, A. Madan, A. Turansky, O. Gluschenkov, R. Lindsay, A. Ajmera, J. Lee, S. Mishra, R. Amos, D. Schepis, H. Ng, and K. Rim, "Design of High Performance PFETs with Strained Si Channel and Laser Anneal", IEDM Tech. Digest, 495 (2005).
  19. M. Horstmann et al. (with S. Panda), "Integration and Optimization of Embedded- SiGe, Compressive and Tensile Liner Films, and Stress Memorization in Advanced SOI CMOS Technlogies", IEDM Tech. Digest, 243 (2005).
  20. P. Bhatnagar, S. Panda, N. Edleman, S. Allen, R. Wise, A. Mahorowala, "Integrated Non-SO2 Underlayer and Improved Line-Edge-Roughness Dielectric Etch Process using 193 nm Bilayer Resist", Appl. Phys. Lett., 88, 231501 (2006).
  21. C. Ouyang et al. (with S. Panda), "Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain", in Transistor Scaling -- Methods, Materials and Modeling, S. Thompson, F. Nouri, W. Tsai, W-C. Lee (Eds.), Mater. Res. Soc. Symp. Proc., 913 (2006).
  22. X. Chen et al. (with S. Panda), "Stress Proximity Technique for Performance Improvement with Dual Stressed Liner at 45nm Technology and Beyond", VLSI Tech. Digest, 60 (2006).
  23. P. Bhatnagar, S. Panda, N. Edleman, S. Allen, R. Wise, A. Mahorowala, "Controlling line-edge roughness and reactive ion etch lag in sub-150 nm features in borophosphosilicate glass", J. Appl. Phys., 101, 076102 (2007).
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