CHE Seminars  

Dr. Siddhartha Panda (IBM Microelectronics, USA)
Fabrication techniques in microelectronics: Etching of dielectrics and silicon
Thursday,  08 June 2004
L-12  Lecture Hall Complex
4.00 to 5.00 p.m.

Some of the unit processes in microchip fabrication are briefly reviewed and the contribution of chemical technology highlighted. Principles of dry etching, one of the fabrication techniques, are discussed. Etch work on two classes of materials are presented. (i) One class is dielectrics, and this presentation is specific to bilayer resist materials. 193 nm lithography single layer resist materials, while enabling printing smaller features than 248 nm materials, have disadvantages of lower etch resistance and lower depth of focus. The bilayer approach, which overcomes some of these limitations, currently uses an O2 based chemistry which in turn has profile control issues. Results of a feasibility study of a non-oxygen containing ammonia based chemistry to etch the bilayer system are presented. (ii) Another class is semiconductors, and this presentation is specific to silicon. Small ground rule (< 0.175 m), high aspect ratio (feature size to depth ratio > 40) trenches in silicon are necessary to achieve required values of cell capacitance in the fabrication of charge-storage capacitors in dynamic random memory devices. Etching of trenches suffers from a dynamic reactive ion etching (RIE) lag mechanism caused by constriction of trench openings during the etch process. Also, at high aspect ratios, reduced ion energy and etchant species flux to the trench bottom (etch front) results in slower etch rates leading to an etch stop. Results of two methods to minimize this problem are presented which increase the differential etch rate of silicon at high aspect ratios, thereby helping achieve higher silicon depths required to meet the device and manufacturing process tool utilization targets.